SoC Team | Senior RTL Design Engineer

Own RTL implementation of assigned SoC blocks for the flight controller chip. Read architecture and micro-architecture specifications, write synthesizable SystemVerilog, close lint/CDC/coverage, and hand off clean RTL to synthesis and physical design. 

• Read and interpret architecture specification documents; implement synthesizable SystemVerilog RTL for assigned blocks. 

• Design FSM (Finite State Machine) logic for control planes: state encoding, transition logic, output decode. 

• Implement datapath blocks: pipelines, arithmetic units, shift registers, mux trees — ensuring correct functional behaviour and timing. 

• Write RTL from specification to silicon-ready code: CAN-FD controller, motor-control PWM timers, IMU SPI/I2C interfaces, AMBA bus fabric glue. 

• Write SVA assertions to capture design intent; work with DV team to achieve functional and code coverage closure. 

• Run CDC/RDC lint and resolve violations; maintain clean coding-guideline compliance. 

• Prepare SDC timing constraints and support synthesis handoff (Synopsys DC/Fusion Compiler or Cadence Genus). 

• Perform DFT insertion for assigned blocks: scan stitching, MBIST hookup, boundary scan. 

• Support ECO implementation and timing-closure iterations with Physical Design team. 

• Maintain block-level micro-architecture documentation and traceability to top-level spec. 

• Bachelor’s or Master’s in Electrical/Computer Engineering. 

• 5+ years RTL design experience in SystemVerilog on commercial SoC tape-outs. 

• Solid synthesizable RTL skills: FSM design, datapath pipelines, Verilog/SystemVerilog coding from specification. 

• Good understanding of Arm Cortex-M/R, AMBA AXI/AHB/APB bus protocols. 

• Familiarity with SVA assertion writing for design verification. 

• Hands-on EDA: Synopsys DC or Cadence Genus for synthesis; VCS or Xcelium for simulation. 

• Basic CDC lint: clock domain crossing analysis and resolution. 

• Basic DFT: scan insertion, ATPG patterns, MBIST. 

• Good English and Vietnamese skills. 

Nice to have:

• Experience implementing CAN-FD controller or motor-control PWM peripheral RTL. 

• RISC-V custom IP or open-source core customization. 

• Familiarity with UPF/CPF low-power design techniques. 

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive compensation package, aligned with capabilities and performance.
• Project bonuses when you join ODC (Offshore Development Center) projects
• Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
• Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
• Access to professional training and development programs within FPT Corporation.
• Working hours: 9:00 AM – 6:00 PM, Monday to Friday.