Global Project | Senior Middle-End Engineer (STA/DFT)

We are looking for a Digital Middle-End Design Engineer with experience in Design for Testability (DFT) and Logic Synthesis.

The ideal candidate should have practical experience with DFT implementation and simulation-based verification, as well as the ability to create SDC constraints for logic synthesis.

• Perform DFT-related design activities involving SCAN, MBIST, and JTAG.
• Execute simulations to verify and validate the functionality of DFT implementations.
• Perform logic synthesis and develop SDC (Synopsys Design Constraints) files.
• Use relevant EDA tools to support digital design and verification activities.
• Collaborate with engineering teams to support project execution and resolve technical issues.

• DFT (Design for Testability)
  • Experience with DFT-related design activities involving:
    • SCAN
    • MBIST (Memory Built-In Self-Test)
    • JTAG (Joint Test Action Group)
  • Ability to execute simulations and verify the functionality of the above DFT features.
• Logic Synthesis
  • Experience with logic synthesis.
  • Ability to create SDC files is mandatory.
• EDA Tools
  • Experience with EDA tools from both Cadence and Synopsys is preferred.

• Good English communication skills; Japanese communication skills are a plus.

Join a supportive and motivated team where your contributions truly matter. As part of our long-term assignment in Japan, you’ll enjoy a range of benefits designed to support both your professional and personal life:

• Housing Allowance: Company sponsored accommodation options or a monthly rental allowance.
• Transportation Allowance: Reimbursement for commuting expenses.
• Performance Bonuses: Based on your contributions and company performance.
• Comprehensive Insurance: Full social and medical coverage in accordance with Japanese labor laws.
• Home Visit Allowance: Financial support for travel back home.
• Family Allowance: Additional benefits for employees and dependents in Japan.