Senior Design Verification Engineer

• Build and maintain SystemVerilog / UVM testbenches for IP/SoC and subsystem blocks.
• Write directed and constrained-random tests to exercise design features.
• Add SVA assertions and functional coverage, and help drive coverage closure.
• Debug failures together with RTL designers and track issues to closure.
• Run and monitor simulation regressions (VCS / Xcelium) and report results.

• Bachelor’s degree in Electronics, Electrical, or Computer Engineering (or a related field).
• 2-7 years of experience in IC / RTL verification.
• Familiar with SystemVerilog; exposure to UVM is a plus (we will help you grow).
• Some hands-on experience with a simulator (VCS, Xcelium, or QuestaSim).
• Good teamwork, eagerness to learn, and basic technical English.

Nice to have:

• Internship or academic project experience in digital design or verification.
• Scripting with Python, Tcl, or shell.

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive salary in labor market
• Project bonuses when you join ODC (Offshore Development Center) projects
• Bonus and welfare policies (FPT Care, summer retreat, teambuilding, annual health check-ups, Training) standardized according to large corporate scale. Access to Up-Skill Training and professional development programs.
• Opportunities to access leading design technologies and participate in Japan & Korea projects in a professional, standardized microcircuit design environment.
• Unlimited development: participate in the value chain from PMIC, IP Solutions, Engineering Service, ATE & Packaging, Camera & Drone to IoT Devices. 
• Working time: 9:00 AM-6:00 PM From Mondays to Fridays