SoC Architecture (AI-on-Edge for Camera Gimbal)

• Define the top-level SoC architecture and microarchitecture for a gimbal/motion-control device, combining an Arm CPU subsystem with an edge-AI accelerator (NPU) and DSP data path.
• Architect the AI/ML inference subsystem for on-device vision (subject detection and tracking): NPU/DSP selection, on-chip memory and bandwidth budgeting, and the dataflow from camera to inference to motor command.
• Define the motor-control architecture for three brushless (BLDC/PMSM) axes — high-resolution PWM timers, synchronized multi-channel ADC current sensing, and the Field-Oriented Control (FOC) compute path.
• Specify the camera and sensor interfaces (parallel DCMI and/or MIPI CSI-2, IMU over SPI/I2C) and the on-chip interconnect (AMBA AXI/AHB/APB), address map, and clock/power-domain structure.
• Drive PPA and dataflow analysis balancing real-time motor-control determinism against AI inference throughput, latency and power within a handheld/embedded thermal and cost budget.
• Lead IP selection and make-vs-buy across CPU, NPU/AI, DSP (e.g. Cadence Tensilica, Synopsys ARC, CEVA), camera (MIPI), ADC and PLL IP, defining integration requirements.
• Author detailed architecture and microarchitecture specifications and partition the design into IP/sub-blocks for RTL and verification teams.
• Collaborate with AI/software and firmware teams on the model-deployment toolchain (quantization, operator support) and the FOC/stabilization firmware library.
• Support RTL, verification, DFT, physical implementation and silicon bring-up as the architectural reference.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.
• 10+ years of digital IC / SoC design experience, with 5+ years in an SoC architecture or lead microarchitecture role (exceptional candidates with fewer years considered).
• Proven experience defining SoC architecture that integrates an AI/NPU or DSP accelerator with a CPU subsystem, from specification through silicon.
• Strong knowledge of edge-AI / ML hardware: NPU/DSP architectures, fixed-point/quantized inference, on-chip memory and bandwidth optimization for neural networks.
• Deep knowledge of Arm CPU architecture and microarchitecture and expert understanding of AMBA (CHI, AXI, AHB, APB) interconnect, address mapping and clock/power domains.
• Knowledge of motor-control and mixed-signal: high-resolution PWM timers, ADC current sensing, and ideally Field-Oriented Control (FOC) of brushless motors.
• Familiarity with camera/imaging interfaces (MIPI CSI-2 / D-PHY, parallel DCMI) and IMU
• Strong grasp of memory subsystems and PPA trade-off analysis 
• Proficiency in SystemVerilog and scripting (Python, PERL, shell) for modeling and flow automation.
• Good English and Vietnamese communication skills, both verbal and written.

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive salary in labor market
• Project bonuses when you join ODC (Offshore Development Center) projects
• Bonus and welfare policies (FPT Care, summer retreat, teambuilding, annual health check-ups, Training) standardized according to large corporate scale. Access to Up-Skill Training and professional development programs.
• Opportunities to access leading design technologies and participate in Japan & Korea projects in a professional, standardized microcircuit design environment.
• Unlimited development: participate in the value chain from PMIC, IP Solutions, Engineering Service, ATE & Packaging, Camera & Drone to IoT Devices. 
• Working time: 9:00 AM-6:00 PM From Mondays to Fridays