Logic Design & Verification Engineer

• Design and verification related to Synopsys IPs (I3C / QSPI / GPIO / CAN / SDIF / JTAG).
• Covering the entire flow from configuration study, implementation, to verification.
• Verification using a UVM-based verification environment.

• Bachelor’s degree in Electronics, Electrical Engineering, Computer Engineering, or equivalent.
• 3+ years of experience in Logic Design & Verification.
• Hands-on experience with Synopsys IP, covering configuration study, implementation, and verification
• Experience in creating verification patterns and executing verification using a UVM-based environment
• Experience in logic development (design and/or verification)
• Practical experience using EDA tools for design and verification (e.g. VCS and other standard tools used in verification workflows)
• Good Japanese communication.
• Good communication skills and ability to work independently

Preferred Qualifications:

• Design and/or verification experience using SystemVerilog
• Experience with IP-XACT
• Verification experience utilizing C / C++
• Experience with formal verification

Join a supportive and motivated team where your contributions truly matter. As part of our long-term assignment in Japan, you’ll enjoy a range of benefits designed to support both your professional and personal life:

• Housing Allowance: Company sponsored accommodation options or a monthly rental allowance.
• Transportation Allowance: Reimbursement for commuting expenses.
• Performance Bonuses: Based on your contributions and company performance.
• Comprehensive Insurance: Full social and medical coverage in accordance with Japanese labor laws.
• Home Visit Allowance: Financial support for travel back home.
• Family Allowance: Additional benefits for employees and dependents in Japan.
• Campaign Go Japan Support: One-time assistance based on role and family status.