TSMC’s 1-nm chip manufacturing process is starting to take shape. After the findings of its collaboration with MIT and the National University of Taiwan (NTU) were made public this summer, TSMC is reportedly planning a 1-nm fab in Taoyuan, Taiwan. According to a report published inTaiwan News, the new 1-nm chip production facility will be located in an industrial park in Longtan District, where TSMC is already running two semiconductor packaging and testing plants.
A lot is going on at the world’s largest pure-play semiconductor fab.TSMC’s 3-nm chips will enter mass production in the fourth quarter of this year, and N3E, an upgraded version of its 3-nm process node, is touted to start commercial production in the second half of 2023. Next, TSMC’s 2-nm chips are being eagerly anticipated by 2025 at its Baoshan facility in Hsinchu. The 2-nm chips are expected to enable 10% to 15% faster processing while using 25% to 30% less power compared to the fab’s 3-nm chips.
TSMC sources are quick to point out that its manufacturing technologies beyond the 3-nm node are in the pathfinding stage currently. However, the fact that TSMC is already working on 1-nm technology is a crucial development.
1-nm technology breakthrough
Further miniaturization of the semiconductor process technologies increases resistance at contacts, so TSMC and other mega fabs are striving to find a contact material that has a very low resistance, can transfer high currents, and can be used for volume production. In May 2022, TSMC announced it has developed key features of the 1-nm process node in collaboration with MIT and NTU, but it’s also clarified that these findings might not necessarily be used in commercial chip production any time soon.
A paper jointly published by MIT, NTU, and TSMC has described the manufacturing challenges caused by metal-induced gaps in conductivity and how monolayer technologies suffer from those metal-induced gaps. Next, it proposes using post-transition metal bismuth and some semi-conductive monolayer transition metal dichalcogenides to reduce the size of the gaps, producing 2D transistors much smaller than had been previously possible.
The breakthrough relates to a new set of materials that can create monolayer—or two-dimensional (2D)—transistors in a chip to scale the overall density by a factor matching the number of layers. The teams at TSMC and MIT have demonstrated low resistance ohmic contacts with a variety of existing semiconductor materials, including molybdenum disulfide (MoS2), tungsten disulfide (WS2), and tungsten diselenide (WSe2).
In short, using non-silicon materials facilitates very tiny transistors—as small as 1 nm. However, as TSMC researchers acknowledge, the 1-nm process node is not likely to be used for years to come. The work to find the right transistor structure, as well as the right transistor materials, for the realization of 1-nm process geometry is an exciting development, nevertheless.
(Source: EDN – https://www.edn.com/tsmc-approaching-1-nm-with-2d-materials-breakthrough)