01. Location : Ho Chi Minh
02. Responsibilities :
- Work with design team to build up SRAM design from spec.
- Participate in floorplanning and layout leafcell implementation.
- Handle layout verification (DRC/LVS/ERC/EMIR) on both leafcell level and top instance level.
- Setup and perform physical QA flow and Compiler integration for tape-out.
- Cooperate with design team on chip level integration of silicon testchip implementation.
- Participate in mentoring junior members.
03. Requirements :
- Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering or relevant.
- Good background of CMOS technology (behavior + characteristic) and logic gate (function, Logic Circuits, Boolean Algebra, and Truth Tables)
- 2Y+ in customized layout implementation. Experience in memory leafcell implementation, optimization, and verification.
- Experience in memory layout floorplaning, power mesh planning, and key layout optimization.
- Good English and communication skills.
04. Benefit & Perks :
Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Competitive salary in labor market.
- 13th month salary.
- “FPT care” health insurance provided by PIJICO and is exclusive for FPT employees.
Recharge and relax with paid annual summer vacation.
05. Contact :
For support and more information, please contact: