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FSEMI – RTL Design engineer


01. Location(s):Da Nang City, Ho Chi Minh City, Ha Noi City

02. Position Type:Employee

03. Job Description:

  • Make design documents, integration guidelines.
  • Write RTL code (Verilog or SystemVerilog)
  • Make IP configuration and generate RTL if the IP is provided from other vendors.
  • Integrate IP into block, then release RTL to build SoC.
  • Cooperate with Verification Team to qualify the design.

04. Requirements:

  • Familiar with RTL/logic design flow and basic knowledge such as FSM, combinational logic, sequential logic, FIFO, etc.
  • Good understanding of Verilog/SystemVerilog for synthesis
  • Good understanding of design techniques such as multi clock domain crossing (CDC), low power, etc.

05. Benefit:

  • Competitive salary and benefits package.
  • Opportunity for growth and advancement within the company.
  • Chance to work on innovative projects and make a meaningful impact in the automotive industry.

06. Contact:

    Send your CV